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The present invention relates to apparatus and methods for accessing electrical nodes of electronic circuits for programming, testing, or debugging purposes.
One way of providing access to electrical nodes of Integrated Circuits (ICs) is commonly referred to as xe2x80x9cscan testing,xe2x80x9d which typically involves serially shifting digital data into state elements included in an IC to apply logic levels to selected nodes as test stimuli, and serially shifting digital date out of the state elements to capture logic levels generated at other nodes in response to the test stimuli. Such control and observation of an IC""s electrical nodes via state elements is also used to provide xe2x80x9cvisibilityxe2x80x9d into an IC for debugging purposes. Further, an IC that supports scan testing is frequently used to access electrical nodes of other electronic circuits connected thereto. For example, these other electronic circuits may be embedded within the IC, i.e., embedded memories or cores, or externally connected to the IC.
Scan testing is typically performed in accordance with the IEEE 1149.1 Standard described in the IEEE 149.1-1990 Standard Test Access Port and Boundary Scan Architecture specification, the entire disclosure of which is incorporated herein by reference. The IEEE 1149.1 Standard was primarily developed to solve problems related to Printed Circuit Board (PCB) testing. The IEEE 1149.1 Standard is also typically used to access xe2x80x9cscan chainsxe2x80x9d within ICs to facilitate testing and debugging of ICs, PCBs, and systems.
xe2x80x9cBoundary scanxe2x80x9d is an application of scan testing at input and output (I/O) pins of an IC to provide direct control and observation of electrical nodes using boundary scan operations. Boundary scan involves a specific type of scan path having a boundary scan register cell at each I/O pin of an IC. For example, by performing boundary scan operations, known logic levels may be placed directly on outputs of one circuit and observed at inputs of another circuit connected thereto. Boundary scan therefore provides a way of determining whether circuits are properly connected to each other on, e. g., a PCB, and/or whether there are manufacturing defects on the PCB that may prevent the circuits from carrying out their intended mission. Boundary scan tests can detect different types of defects on a PCB, e.g., broken circuit traces, cold solder joints, solder bridges, and electrostatic-discharge (ESD) induced failures in IC buffers.
FIG. 1 depicts boundary scan architecture 100, which is compliant with the IEEE 1149.1 Standard and may be embedded in an IC to provide direct control and observation of electrical nodes via the IC""s I/O pins. As depicted in FIG. 1, an IC compliant with the IEEE 1149.1 Standard includes the following four (4) mandatory pins: TDI, TDO, TCK, and TMS. Further, the IC optionally includes the pin, TRSTN. These pins, TDI, TDO, TCK, TMS, and optionally TRSTN, are commonly known as the Test Access Port (TAP).
In addition, the IC includes three (3) mandatory scan registers, i.e., an Instruction Register (IR) 104; and, two (2) Data Registers (DRs), i.e., a Boundary Scan Register (BSR) 106 and a Bypass Register (BYPASS) 108. Further, the IC optionally includes at least one User DR, i.e., a User DR 110, which may be used to implement tests such as internal scan path testing and Built-In Self-Test. (BIST). Moreover, the IC includes a protocol interface 102 known as a TAP Controller, which includes a 16-state Finite State Machine (FSM) operated by the mandatory TMS and TCK input pins and other logic.
FIG. 3 depicts a state diagram 300 for the standard FSM of the Tap Controller 102. A logic level on the TMS pins determines a next state of the FSM, and a clock signal on the TCK pin causes state transitions to occur. Further, an updated IR instruction selects the IR 104, the BSR 106, the BYPASS DR 108, or the USER DR 110 for scan operations. Moreover, the FSM includes a Select-DR branch 301 that defines states for performing a xe2x80x9cDR-scanxe2x80x9d operation and a Select-IR branch 303 that defines states for performing an xe2x80x9cIR-scanxe2x80x9d operation.
The IR 104, the BSR DR 106, the BYPASS DR 108, and the USER DR 110 each comprise a separate scan path; and, the TAP Controller 102 enables operation of only one of these scan registers at a time. The selected scan register shifts its scan data between the TDI pin and the TDO pin during a Shift-IR 324 state or a Shift-DR 310 state. Further, the selected scan register for the next set of scan operations is determined by the IR instruction that was previously updated in the IR 104 during an Update-IR 332 state. Moreover, the IEEE 1149.1 Standard uses both edges of the clock signal on the TCK pin. Specifically, a logic level on the TMS pin and scan data on the TDI pin are sampled on the rising edge of the clock signal, and scan data on the TDO pin changes on the falling edge of the clock signal.
The state diagram 300 of FIG. 3 includes six (6) xe2x80x9csteady-states,xe2x80x9d i.e., a Test-Logic-Reset 302 state, a Run-Test/Idle 304 state, a Shift-DR 310 state, a Pause-DR 314 state, a Shift-IR 324 state, and a Pause-IR 328 state. According to the IEEE 1149.1 Standard, there is only one (1) steady-state when the TMS pin is set to logical 1, i.e., the Test-Logic-Reset 302 state; and, the FSM of the TAP Controller 102 can be reset (i.e., transition to the Test-Logic-Reset 302 state) within five (5) TCK clock signal transitions while the TMS pin is set to logical 1. The optional TRSTN pin provides another way to reset the FSM of the TAP Controller 102. For example, setting the TRSTN pin to logical 0 causes an asynchronous reset of the TAP Controller 102 FSM.
The DR branch 301 and the IR branch 303 of the TAP Controller 102 FSM each includes six (6) states. Specifically, a Capture state, e.g., a Capture-DR 308 state and a Capture-IR 322 state, causes a selected scan register to capture data via parallel inputs of the scan register. This captured data is shifted out of the selected register on the TDO pin during the Shift-DR 310 state or the Shift-IR 324 state, while new scan data is simultaneously shifted into the register via the TDI pin.
After the scan shift operation is completed, new scan data is updated into a parallel update stage of the scan register. An IR or DR update operation is enabled upon entering either the Update-IR 332 state or the Update-DR state 318, respectively.
A state sequence including an Exit1-DR 312 state, immediately followed by a Pause-DR 314 state, and immediately followed by an Exit2-DR 316 state is used to terminate or suspend the Shift-DR 310 state operation. Similarly, a state sequence including an Exit1-IR 326 state, immediately followed by a Pause-IR 328 state, and immediately followed by an Exit2-IR 330 state is used to terminate or suspend the Shift-IR 324 state operation. The Pause-DR 314 state and the Pause-IR 328 state are included in the TAP Controller 102 FSM primarily to account for potentially slow tester hardware and/or software performance.
The instructions updated in the IR 104 not only select scan registers for shifting scan data, but also determine test behavior, e.g., for boundary scan testing of PCB interconnects. The IEEE 1149.1 Standard specifies three (3) mandatory instructions and their corresponding test behavior. One such instruction is the BYPASS instruction, which selects the BYPASS DR 108 to provide a 1-bit scan path between TDI and TDO. For example, scan paths of multiple circuits compliant with the IEEE 1149.1 Standard may be chained together by serially connecting their respective TDI and TDO pins. The BYPASS instruction may then be used to xe2x80x9cbypassxe2x80x9d these potentially long scan paths when DRs corresponding thereto do not have to be accessed for particular test or debug operations. In this way, the BYPASS instruction(s) may be used to reduce the number of scan bits that are shifted.
Other mandatory instructions are the SAMPLE/PRELOAD and EXTEST instructions, both of which select the BSR 106. Specifically, the SAMPLE/PRELOAD instruction is used to sample logic levels on an IC""s I/O pins during normal operation and pre-load data into the BSR 106 before testing. The IC""s I/O pins are controlled by normal system logic during the SAMPLE/PRELOAD instruction. The EXTEST instruction controls the IC""s I/O pins from the BSR 106 and may be used to perform PCB interconnect testing.
Although the boundary scan architecture 100 can be used to program, test, and debug electronic circuits, the boundary scan architecture 100 has several drawbacks. For example, in accordance with the IEEE 1149.1 Standard, the Pause-IR 328 state and the Pause-DR 314 state are included in the Select-IR branch 303 and the Select-DR branch 301, respectively, of the TAP Controller 102 FSM primarily to account for less than optimal tester hardware and/or software performance. However, the hardware and software of today""s test resources are normally fast enough to shift scan data continuously without requiring the Pause-IR 328 and Pause-DR 314 states. Accordingly, these states merely increase the time required to perform such shift operations.
In addition, in ICs compliant with the IEEE 1149.1 Standard and PCBs including such components, it is frequently difficult to access electrical nodes of non-scan sequential circuits from scan paths surrounding these circuits. Such non-scan sequential circuits may include non-scan embedded cores and component clusters on PCBs. The IEEE 1149.1 Standard is particularly inefficient when used to access memories, whether the memories are embedded within an IC or externally connected to an IC. This is because memories typically require long and/or complex control and address sequences to fully access their contents and provide comprehensive testing thereof, and ICs compliant with the IEEE 1149.1 Standard often cannot efficiently handle such long and complex sequences.
Specifically, if the BSR 106 of an IC were used to move data to a memory externally connected to the IC, then read/write cycles of the memory would typically be emulated using the Select-DR branch 301 of the TAP Controller 102 FSM, and data would typically be shifted into the BSR 106 to sequence the data, address, and control signals of the memory. This is conventionally done by putting the IC into the EXTEST mode, shifting a pattern of address, data, and control values into corresponding bit positions of the BSR 106, and updating the BSR 106 to apply the bit pattern to the memory in parallel.
However, any change in a control value, e.g., to place a logical 0 on a write enable (WEN) pin, therefore requires multiple BSR shift operations. This can be very inefficient for complex access sequences, wherein several BSR scan operations may be required to read from or write to a single address location of the memory. Further, read/write control sequences must be serialized to apply these same sequences through the BSR 106.
Still further, each BSR scan operation scans all of the bits in the BSR 106, not just those bits needed to access the memory data, address, and control signals. This also decreases efficiency because in a typical IC with high-density I/O packaging, e.g., a Ball Grid Array (BGA), the BSR 106 can be several hundred bits in length yet only a fraction of these bits typically needs to be accessed to control the memory signals.
In addition, the protocol of the TAP Controller 102 FSM prohibits certain types of testing. Specifically, the TAP Controller 102 FSM does not provide for a state sequence including the Shift-DR state, immediately followed by the Capture-DR state, and immediately followed by the Shift-DR state, which is normally required for controlling internal scan registers; or, a state sequence including the Update-DR state immediately followed by the Capture-DR state, which is normally required for performing path delay testing of interconnects.
It would therefore be desirable to have improved apparatus and methods that provide for the access of electrical nodes of electronic circuits including scan and non-scan sequential circuits and combinatorial circuits. It would also be desirable to have improved apparatus and methods that efficiently access electrical nodes of electronic circuits that require long and/or complex control and address sequences.
In accordance with the present invention, apparatus and methods are disclosed for providing optimized access to electrical nodes of electronic circuits for programming, testing, and debugging. The presently disclosed apparatus includes an access interface circuit that can be connected between a test resource and an electronic circuit such as a circuit adapted for scan testing, a non-scan sequential circuit, a component cluster, or a memory circuit. The access interface circuit includes a protocol generator, which has a control register queue and an address register; and, a data generator, which has a plurality of registers adapted for capturing, shifting, and/or updating data samples. Address and control sequences for programming/testing/debugging the electronic circuit can be serially loaded into the control register queue and the address register using the test resource. Data sequences for programming/testing/debugging the electronic circuit can also be serially loaded into the data registers using the test resource. The access interface circuit also includes circuitry for switchably and directly applying either the serially loaded address and control sequences or the normal system address and control signals to the electronic circuit; and, for switchably and directly applying either the serially loaded data sequences or the normal system data signals to the electronic circuit. The access interface circuit further includes circuitry for directly capturing data values from the electronic circuit in the data registers. The access interface circuit therefore allows complex access sequences to be efficiently applied to the electronic circuit, and data sequences to be efficiently written to and read from the electronic circuit under control of the test resource. Such capability is particularly useful in programming/testing/debugging memory and non-scan circuits.
The presently disclosed apparatus further includes a programmable controller connected to the access interface circuit and connectable to the test resource. The programmable controller includes a state machine having a plurality of states at least one of which is programmable. The access interface circuit performs operational commands based on at least a portion of the plurality of states. Because the state machine is programmable, the programmable controller enhances the flexibility of the access interface circuit for programming/testing/debugging electronic circuits. The access interface circuit also includes at least one scan path connectable to the electronic circuit; and, circuitry for switchably applying, under control of the programmable controller, address/control sequences from the protocol generator, data sequences from the data generator, and/or data sequences from the test resource to the scan path. The control register queue and address register of the protocol generator and the data registers of the data generator comprise minimal length scan paths that can be used for efficiently programming/testing/debugging the circuits adapted for scan testing.
The access interface circuit and/or the programmable controller may be controlled by way of the test resource to enable communication between the test resource and the electronic circuit connected to the access interface circuit. The test resource can be any type of apparatus customarily used to program/test/debug electronic circuits, such as Automatic Test Equipment (ATE) or a general-purpose computer, e.g., a Personal Computer (PC), connected to the access interface circuit. Alternatively, the test resource may be embedded with the access interface circuit and the programmable controller in a device such as an IC.
The access interface circuit and/or the programmable controller may be designed into a device as a permanent/fixed interface; or, in the case of a programmable logic device such as a Field Programmable Gate Array (FPGA), the access interface/programmable controller may be temporarily programmed into the device. By utilizing the latter method, electronic circuits coupled to the access interface may be temporarily accessed for programming/testing/debugging purposes via the FPGA, and the FPGA can be subsequently re-programmed with its normal mission mode logic.
Other features, functions, and aspects of the access interface will be evident from the Detailed Description of the Invention that follows.